feat: add experimental VHDL support

.github/workflows/test.yaml

@@ -9,9 +9,9 @@ jobs:
         with:
           submodules: recursive
 
-      - name: Install iverilog
+      - name: Install iverilog & ghdl
         shell: bash
-        run: sudo apt-get update && sudo apt-get install -y iverilog
+        run: sudo apt-get update && sudo apt-get install -y iverilog ghdl-llvm
 
       # Set Python up and install cocotb
       - name: Setup python
@@ -23,6 +23,21 @@ jobs:
         shell: bash
         run: pip install -r test/requirements.txt
 
+      - name: Checkout tt-support-tools repo
+        uses: actions/checkout@v4
+        with:
+          repository: TinyTapeout/tt-support-tools
+          path: tt
+          ref: tt09
+
+      - name: Install tt-support-tools dependencies
+        shell: bash
+        run: pip install -r tt/requirements.txt
+
+      - name: Run tt_tool.py to transpile .vhdl to .v
+        shell: bash
+        run: ./tt/tt_tool.py
+
       - name: Run tests
         run: |
           cd test

.gitignore

@@ -3,6 +3,7 @@
 *.vcd
 runs
 tt_submission
+src/generated/
 src/user_config.json
 src/config_merged.json
 test/sim_build

README.md

@@ -1,6 +1,6 @@
 ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+# Tiny Tapeout VHDL Project Template (experimental)
 
 - [Read the documentation for project](docs/info.md)
 
@@ -10,9 +10,9 @@ Tiny Tapeout is an educational project that aims to make it easier and cheaper t
 
 To learn more and get started, visit https://tinytapeout.com.
 
-## Set up your Verilog project
+## Set up your VHDL project
 
-1. Add your Verilog files to the `src` folder.
+1. Add your VHDL files to the `src` folder.
 2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
 3. Edit [docs/info.md](docs/info.md) and add a description of your project.
 4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.

info.yaml

@@ -4,7 +4,7 @@ project:
   author:       ""      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "VHDL"  # other examples include Verilog, SystemVerilog, Amaranth, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
@@ -17,7 +17,7 @@ project:
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "project.vhdl"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/project.vhdl

@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity tt_um_example is
+    port (
+        ui_in   : in  std_logic_vector(7 downto 0);
+        uo_out  : out std_logic_vector(7 downto 0);
+        uio_in  : in  std_logic_vector(7 downto 0);
+        uio_out : out std_logic_vector(7 downto 0);
+        uio_oe  : out std_logic_vector(7 downto 0);
+        ena     : in  std_logic;
+        clk     : in  std_logic;
+        rst_n   : in  std_logic
+    );
+end tt_um_example;
+
+architecture Behavioral of tt_um_example is
+begin
+
+    uo_out <= std_logic_vector(unsigned(ui_in) + unsigned(uio_in));
+    uio_out <= "00000000";
+    uio_oe <= "00000000";
+
+end Behavioral;

test/Makefile

@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = generated/project.v
 
 ifneq ($(GATES),yes)