From 6eb37c37a3bc035d11e2e56cecaa6f9375e59c28 Mon Sep 17 00:00:00 2001 From: htfab Date: Mon, 30 Sep 2024 17:45:37 +0200 Subject: [PATCH] feat: add experimental VHDL support --- .github/workflows/test.yaml | 19 +++++++++++++++++-- .gitignore | 1 + README.md | 6 +++--- info.yaml | 4 ++-- src/project.v | 27 --------------------------- src/project.vhdl | 25 +++++++++++++++++++++++++ test/Makefile | 2 +- 7 files changed, 49 insertions(+), 35 deletions(-) delete mode 100644 src/project.v create mode 100644 src/project.vhdl diff --git a/.github/workflows/test.yaml b/.github/workflows/test.yaml index cb31af4..3657a27 100644 --- a/.github/workflows/test.yaml +++ b/.github/workflows/test.yaml @@ -9,9 +9,9 @@ jobs: with: submodules: recursive - - name: Install iverilog + - name: Install iverilog & ghdl shell: bash - run: sudo apt-get update && sudo apt-get install -y iverilog + run: sudo apt-get update && sudo apt-get install -y iverilog ghdl-llvm # Set Python up and install cocotb - name: Setup python @@ -23,6 +23,21 @@ jobs: shell: bash run: pip install -r test/requirements.txt + - name: Checkout tt-support-tools repo + uses: actions/checkout@v4 + with: + repository: TinyTapeout/tt-support-tools + path: tt + ref: tt09 + + - name: Install tt-support-tools dependencies + shell: bash + run: pip install -r tt/requirements.txt + + - name: Run tt_tool.py to transpile .vhdl to .v + shell: bash + run: ./tt/tt_tool.py + - name: Run tests run: | cd test diff --git a/.gitignore b/.gitignore index 8746fa0..836dea2 100644 --- a/.gitignore +++ b/.gitignore @@ -3,6 +3,7 @@ *.vcd runs tt_submission +src/generated/ src/user_config.json src/config_merged.json test/sim_build diff --git a/README.md b/README.md index 68ba6ed..2238051 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg) -# Tiny Tapeout Verilog Project Template +# Tiny Tapeout VHDL Project Template (experimental) - [Read the documentation for project](docs/info.md) @@ -10,9 +10,9 @@ Tiny Tapeout is an educational project that aims to make it easier and cheaper t To learn more and get started, visit https://tinytapeout.com. -## Set up your Verilog project +## Set up your VHDL project -1. Add your Verilog files to the `src` folder. +1. Add your VHDL files to the `src` folder. 2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/). 3. Edit [docs/info.md](docs/info.md) and add a description of your project. 4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information. diff --git a/info.yaml b/info.yaml index 50bb751..adae7b4 100644 --- a/info.yaml +++ b/info.yaml @@ -4,7 +4,7 @@ project: author: "" # Your name discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) description: "" # One line description of what your project does - language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc + language: "VHDL" # other examples include Verilog, SystemVerilog, Amaranth, etc clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) # How many tiles your design occupies? A single tile is about 167x108 uM. @@ -17,7 +17,7 @@ project: # Source files must be in ./src and you must list each source file separately, one per line. # Don't forget to also update `PROJECT_SOURCES` in test/Makefile. source_files: - - "project.v" + - "project.vhdl" # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: diff --git a/src/project.v b/src/project.v deleted file mode 100644 index cd6f740..0000000 --- a/src/project.v +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2024 Your Name - * SPDX-License-Identifier: Apache-2.0 - */ - -`default_nettype none - -module tt_um_example ( - input wire [7:0] ui_in, // Dedicated inputs - output wire [7:0] uo_out, // Dedicated outputs - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - input wire ena, // always 1 when the design is powered, so you can ignore it - input wire clk, // clock - input wire rst_n // reset_n - low to reset -); - - // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; - assign uio_oe = 0; - - // List all unused inputs to prevent warnings - wire _unused = &{ena, clk, rst_n, 1'b0}; - -endmodule diff --git a/src/project.vhdl b/src/project.vhdl new file mode 100644 index 0000000..4d5c044 --- /dev/null +++ b/src/project.vhdl @@ -0,0 +1,25 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity tt_um_example is + port ( + ui_in : in std_logic_vector(7 downto 0); + uo_out : out std_logic_vector(7 downto 0); + uio_in : in std_logic_vector(7 downto 0); + uio_out : out std_logic_vector(7 downto 0); + uio_oe : out std_logic_vector(7 downto 0); + ena : in std_logic; + clk : in std_logic; + rst_n : in std_logic + ); +end tt_um_example; + +architecture Behavioral of tt_um_example is +begin + + uo_out <= std_logic_vector(unsigned(ui_in) + unsigned(uio_in)); + uio_out <= "00000000"; + uio_oe <= "00000000"; + +end Behavioral; \ No newline at end of file diff --git a/test/Makefile b/test/Makefile index 6fdbe36..b87f337 100644 --- a/test/Makefile +++ b/test/Makefile @@ -5,7 +5,7 @@ SIM ?= icarus TOPLEVEL_LANG ?= verilog SRC_DIR = $(PWD)/../src -PROJECT_SOURCES = project.v +PROJECT_SOURCES = generated/project.v ifneq ($(GATES),yes)